// Sequence Detector V1: Encoding Transition Table

`timescale 1ns/1ns
module SequenceDetectorV1(clk, in, out);
	input clk;
	input in;
	output out;
	
	reg [1:0] Q;

// Initial state
	initial Q = 2'b00;

// Next-state logic: assign
//
	wire [1:0] D;
	assign D[1] = in & (Q[1] | Q[0]);
	assign D[0] = in & (Q[1] | ~Q[0]);
//

// Next-atate logic: always
/*
	reg [1:0] D;
	always @*
	begin
		D[1] <= in & (Q[1] | Q[0]);
		D[0] <= in & (Q[1] | ~Q[0]);
	end
*/

// State Update
	always @(posedge clk)
		Q <= D;

// Output logic
	assign out = (Q[1] & Q[0]);
endmodule