// Sequence Detector V2: Encoding Transition List
`timescale 1ns/1ns 
module SequenceDetectorV2(clk,in, out);
	input clk;
	input in;
	output out;
	
	reg [1:0] Q;
	reg [1:0] D;				// Q_Next = D

	parameter zero1s	= 2'b00;
	parameter one1		= 2'b01;
	parameter two1s		= 2'b10;
	parameter three1s	= 2'b11;
	
// Initial state
	initial Q = zero1s;
	
// State Transitions
	always @*
	//begin
		case(Q)
			zero1s:	if (in)
								D <= one1;
							else
								D <= zero1s;
			one1:		if (in)
								D <= two1s;
							else
								D <= zero1s;
			two1s:	if (in)
								D = three1s;
							else
								D <= zero1s;
			three1s: if (in)
								D <= three1s;
							else
								D <= zero1s;
		endcase
//	end
	
// State Update
	always @(posedge clk)
		Q <= D;

// Output logic
	assign out = (Q == three1s);
endmodule