File Name: TestBench6.v
`timescale 1s/100ms
module TestBench6();
	reg CLK;
	reg [17:0] SW; 							// E = SW[3], NL = SW[2], EL = SW[1], W = SW[0], Reset = SW[17]
	wire [6:0] HEX7, HEX6;	// Timer
	wire [6:0] HEX3;				// ETL
	wire [6:0] HEX2;				// NLTL
	wire [6:0] HEX1;				// ELTL
	wire [6:0] HEX0;				// WTL

	wire [3:0] RemainingTime;

// Instantiate the TLC module

// Define Clock

// Reset and start simulation
	initial
	begin

	end
//
endmodule // TestBench6