eecs270.org
EECS 270: Introduction to Logic Design
The University of Michigan, Fall 2026
This site/course is currently being revised for Fall 2026; availability of the final version of the Fall 2026 syllabus will be announced shortly after the semester begins.
EECS 270 introduces you to the exciting world of digital logic design. Digital devices have proliferated in the last quarter century and have become essential in just about anything we do or depend on in a modern society. Computers of all varieties are now at the heart of commerce, communications, education, health care, entertainment, defense, etc. Personal computers have become standard fixtures in most homes and schools. But while the computer is the most visible digital computing device, it is by no means the only one. Embedded digital controllers can be found in such diverse applications as automobiles, airplanes, elevators, cellphones, televisions, cameras, and many kitchen appliances, to name just a tiny few.
This course provides you with a basic understanding of what digital devices are, how they operate, and how they can be designed to perform useful functions. It forms the foundation for the more advanced hardware courses in our CS, CE, and EE curricula, notably EECS 373, 427, and 470. You will learn about digital design through a combination of lectures, labs, and projects. Through the projects, you will learn to apply the concepts learned in lecture to design real digital circuits using modern design tools and FPGAs.
Attendance Policy
In-person attendance is required. Lectures will be automatically recorded but should not be used as a substitute for lecture attendance. Lectures cannot be attended remotely via Zoom. Lab sessions require attendance, and labs are graded. Please ensure that you attend the section for which you are registered.
Course Topics
- Bits Everywhere!
- Timing and Delay
- Boolean Algebra
- Switching Functions
- Positive Binary Numbers
- Binary Arithmetic
- Combinational Blocks
- Latches and Flip-Flops
- Sequential Circuit Analysis
- Sequential Circuit Design
- Two-Level Logic Minimization
- Sequential Building Blocks
- Register Transfer Level (RTL) Design
- Sequential Timing Analysis
- Sequential Multiplication
- Algorithmic Two-Level Logic Minimization
- Designing Fast Adders
- State Assignment and Minimization
Optional Textbooks
- F. Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd ed., Wiley.
- J. F. Wakerly, Digital Design: Principles and Practices, 4th ed., Prentice-Hall.
- J. P. Hayes, Introduction to Digital Logic Design, Addison-Wesley.
- C. H. Roth, Jr., Fundamentals of Logic Design.
- R. H. Katz, Contemporary Logic Design, Prentice-Hall.
- D. Thomas, P. Moorby, The Verilog Hardware Description Language.
Projects
You will complete seven projects through the semester. In these projects, you will design and implement various digital circuits for deployment on the DE2-115 FPGA development board.
The projects increase in complexity as the semester progresses. The first four projects focus on combinational logic design, while the last three projects focus on sequential logic design. You will use Verilog as the hardware description language (HDL) for all projects.
For further details on the projects, please refer to the Projects Overview page.
Labs
Lab sessions are 110 minutes, starting at the scheduled time. Course staff facilitate labs and are available for questions. Attendance and participation in lab is required to earn credit. Make sure to bring a suitable laptop or tablet to lab for completing exercises. There are no make-ups for missed lab periods. The lowest two lab grades are automatically dropped for every student. These two drops allow every student two ‘no excuse required’ absences, if needed.
Missing your scheduled lab period
We drop the lowest 2 lab scores for all students. This policy is intended to cover situations in which you must miss a lab due to e.g. a planned medical procedure, an unanticipated medical or personal emergency, or an official university conflict. If (and only if) you have already used your two drops, you may petition for an additional drop in cases of illness or emergency. Requests will be considered on a case-by-case basis.
Extensions and Exceptions
Labs and Projects have an “expected” due date and a “no-credit” deadline. There is no penalty for turning in late work after the expected due date if before the no-credit deadline. Project and lab submissions are not allowed past the published no-credit deadline, except in the circumstances outlined below. Please note that, to be granted, exceptions must generally demonstrate an emergency that impacts ability to meet the expected due date that extends through the period to the no-credit deadline. Submit extension/exception requests via the administrative request forms.
Retaking the course
If you are retaking the course, you may reuse your own work and feedback from previous terms. We strongly recommend, however, that you restart labs and projects to ensure your best learning experience. It is students’ responsibility to check whether assignments have changed from one term to the next. Do not assume your projects/labs from a previous term entirely meet the specifications in a new term.
Quizzes and Examinations
Quizzes/examinations may sometimes be conducted through written examination and sometimes through computerized testing (online or at a computerized testing facility on campus). Quizzes/exams may sometimes be conducted in class and sometimes conducted outside of normal class hours (e.g. scheduled out-of class common midterm or final examantions). Specifics on the mode and time for each assessment will be communicated to in class, and via email/Canvas/website.
Regrades
Assessments graded by hand will provide an opportunity for students to request a regrade to correct grading errors. If requested, we will regrade the entire problem and fix any mistakes (the marks awarded may go up or down). Assessments or portions of assessments that are automatically graded (e.g. projects) do not allow for regrade requests.
Late Adds
Students adding EECS 270 late may petition for additional time to turn in assignments.
Planned Exceptions
We will consider extension requests made at least two weeks in advance, for example, for religious holidays or planned medical procedures.
Emergencies
If you experience a medical or personal emergency, please reach out to us! We will consider exceptions on a case-by-case basis. Please provide documentation of the emergency. Requests must be made at least 24 hours before the assignment deadline, unless the emergency prevents prompt communication to course faculty or staff.
Grading
Grade Breakdown
Your final grade will be determined based on the following components:
| Component | Weight |
|---|---|
| Labs | 10% |
| Projects | 30% |
| Midterm 1 | 20% |
| Midterm 2 | 20% |
| Final Exam | 20% |
The 2 lowest lab grades will be dropped from your final grade calculation.
Letter Grade Scale
Your final letter grade will be determined based on your overall percentage in the course, according to the following scale:
| Percentage | Letter Grade |
|---|---|
| 100% - 97% | A+ |
| 97% - 93% | A |
| 93% - 90% | A- |
| 90% - 87% | B+ |
| 87% - 83% | B |
| 83% - 80% | B- |
| 80% - 77% | C+ |
| 77% - 70% | C |
| 70% - 60% | C- |
| 60% - 50% | D |
| Below 50% | E |
Academic Integrity
We encourage collaboration in EECS 270, especially on concepts, tools, specifications, and strategies. However, all submitted work must be your own.
If you are unsure about what constitutes collaboration versus copying, please ask a member of the teaching staff for clarification.
| Encouraged Collaboration | Unacceptable Collaboration |
|---|---|
| Sharing high-level design strategies, e.g., module organization | Walking through a design or module step-by-step, sharing pseudocode, sharing comments |
| Helping others understand the spec or project nuances | Providing your code as a reference |
| Helping someone debug | Debugging someone’s code for them |
| Explaining a synthesis error to someone | Fixing a synthesis error for someone |
| Discussing test strategies | Sharing test code to verify someone else’s design, even if test cases are not submitted |
| Brainstorming edge cases for testing | Discussing specifics about what tests exposed instructor bugs on the autograder |
| Using starter code provided with a project or based on examples shown in lecture | Copying code in whole or in part, even if the code is modified \n Writing original code for someone else, or paying someone to write your project |
| Sharing your code in a way that could be copied, e.g., sending code over email or taking a picture of code |
Code Reuse
Reusing code (your own or other students’) from previous semesters is not permitted.
Publishing Code
Any code you write for this course must not be published in any way or form, including posting on public repositories (e.g., GitHub, GitLab) or personal websites.
Generative AI Policy
The use of generative AI tools is not permitted for writing code or completing assignments in this course.