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EECS 270: Introduction to Logic Design
The University of Michigan, Fall 2025 EECS 270 introduces you to the exciting world of digital logic design. Digital devices have proliferated in the last quarter century and have become essential in just about anything we do or depend on in a modern society. Computers of all varieties are now at the heart of commerce, communications, education, health care, entertainment, defense, etc. Personal computers have become standard fixtures in most homes and schools. But while the computer is the most visible digital computing device, it is by no means the only one. Embedded digital controllers can be found in such diverse applications as automobiles, airplanes, elevators, cellphones, televisions, cameras, and many kitchen appliances, to name just a tiny few.
This course provides you with a basic understanding of what digital devices are, how they operate, and how they can be designed to perform useful functions. It forms the foundation for the more advanced hardware courses in our CS, CE, and EE curricula, notably EECS 373, 427, and 470. You will learn about digital design through a combination of lectures, labs, and projects. Through the projects, you will learn to apply the concepts learned in lecture to design real digital circuits using modern design tools and FPGAs.
Attendance Policy
In-person attendance is required. Lectures will be automatically recorded but should not be used as a substitute for lecture attendance. Lectures cannot be attended remotely via Zoom. Lab sessions require attendance, and labs are graded. Please ensure that you attend the section for which you are registered.
Course Topics
- Bits Everywhere!
- Timing and Delay
- Boolean Algebra
- Switching Functions
- Positive Binary Numbers
- Binary Arithmetic
- Combinational Blocks
- Latches and Flip-Flops
- Sequential Circuit Analysis
- Sequential Circuit Design
- Two Level Logic Minimization
- Sequential Building Blocks
- Register Transfer Level (RTL) Design
- Sequential Timing Analysis
- Sequential Multiplication
- Algorithmic Two-Level Logic Minimization
- Designing Fast Adders
- State Assignment and Minimization
Projects
You will complete seven projects through the semester. In these projects, you will design and implement various digital circuits for deployment on the DE2-115 FPGA development board.
The projects increase in complexity as the semester progresses. The first four projects focus on combinational logic design, while the last three projects focus on sequential logic design. You will use Verilog as the hardware description language (HDL) for all projects.
For further details on the projects, please refer to the Projects Overview page.
Optional Textbooks
- F. Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd ed., Wiley.
- J. F. Wakerly, Digital Design: Principles and Practices, 4th ed., Prentice-Hall.
- J. P. Hayes, Introduction to Digital Logic Design, Addison-Wesley.
- C. H. Roth, Jr., Fundamentals of Logic Design.
- R. H. Katz, Contemporary Logic Design, Prentice-Hall.
- D. Thomas, P. Moorby, The Verilog Hardware Description Language.
Grading
Grade Breakdown
Your final grade will be determined based on the following components:
| Component | Weight |
|---|---|
| Quizzes | 5% |
| Labs | 5% |
| Projects | 30% |
| Midterm 1 | 20% |
| Midterm 2 | 20% |
| Final Exam | 20% |
The 5 lowest quizzes will be dropped from your final grade calculation. The 2 lowest lab grades will also be dropped.
Letter Grade Scale
Your final letter grade will be determined based on your overall percentage in the course, according to the following scale:
| Percentage | Letter Grade |
|---|---|
| 100% - 95% | A+ |
| 95% - 85% | A |
| 85% - 81% | A- |
| 81% - 78% | B+ |
| 78% - 75% | B |
| 75% - 71% | B- |
| 71% - 68% | C+ |
| 68% - 65% | C |
| 65% - 60% | C- |
| 60% - 57% | D+ |
| 57% - 54% | D |
| 54% - 50% | D- |
| Below 50% | E |
Academic Integrity
We encourage collaboration in EECS 270, especially on concepts, tools, specifications, and strategies. However, all submitted work must be your own.
If you are unsure about what constitutes collaboration versus copying, please ask a member of the teaching staff for clarification.
| Encouraged Collaboration | Unacceptable Collaboration |
|---|---|
| Sharing high-level design strategies, e.g., module organization | Walking through a design or module step-by-step, sharing pseudocode, sharing comments |
| Helping others understand the spec or project nuances | Providing your code as a reference |
| Helping someone debug | Debugging someone’s code for them |
| Explaining a synthesis error to someone | Fixing a synthesis error for someone |
| Discussing test strategies | Sharing test code to verify someone else’s design, even if test cases are not submitted |
| Brainstorming edge cases for testing | Discussing specifics about what tests exposed instructor bugs on the autograder |
| Using starter code provided with a project or based on examples shown in lecture | Copying code in whole or in part, even if the code is modified \n Writing original code for someone else, or paying someone to write your project |
| Sharing your code in a way that could be copied, e.g., sending code over email or taking a picture of code |
Code Reuse
Reusing code (your own or other students’) from previous semesters is not permitted.
Publishing Code
Any code you write for this course must not be published in any way or form, including posting on public repositories (e.g., GitHub, GitLab) or personal websites.
Generative AI Policy
The use of generative AI tools is not permitted for writing code or completing assignments in this course.