eecs270.org

ModelSim Quick Start

ModelSim is the simulator officially supported by EECS 270. It runs on CAEN lab machines (in person or via VNC). For a local alternative using iverilog + gtkwave/VaporView, see the Local Simulation Tools Setup Guide.

This page walks through simulating Project 0 in ModelSim. The same steps apply to every project but with modified file names.

Create a ModelSim Project

1. Start ModelSim. On CAEN, launch it from the start menu or terminal.
2. File → New → Project.
   • Project name: Project0
   • Project location: a folder on your N: drive (e.g. N:/270_projects). ModelSim creates the directory if needed.
     • Do not use the local C: drive on CAEN - your work won’t persist across machines.
     • Do not use a cloud drive (e.g., Dropbox, Google Drive) - ModelSim will become unusably slow.
   • Leave the default library name as work.
   • Click OK.
3. Project → Add to Project → Existing File… and add Project0.v, TestBench0.v, and Majority.v.

The Project tab should now list your three files with ? next to each, indicating they are uncompiled.

Compile

1. Select all three files.
2. Right-click → Compile → Compile Selected.
   • You can also use Compile All, though it will generally be a little slower.
3. On success, each file gets a green check mark. On failure, a red X appears next to the offending file. Read the error in the transcript pane, fix the source, and recompile.

Simulate

1. Click the Library tab.
2. Expand the work library, highlight TestBench0, right-click → Simulate.
3. ModelSim opens the simulation view. If the Wave pane is not visible, open it with View → Wave.

Add signals to the waveform

• In the Objects pane, right-click the signals you want to observe (e.g., SW, LEDG) and Add → To Wave → Selected Signals.
  • You can also add internal signals (e.g., Majority/a) by right-clicking the + icon next to the top-module in the Objects pane and selecting the submodule you want. This is critical for debugging.
• Set the run length (e.g., 100 ns) and click the Run icon. The run length should be long enough for all the testbench stimulus to complete.

You should see waveforms showing LEDG[0] going high whenever two or more bits of SW are high.

Save your wave configuration

In the Wave pane: File → Save Format → save as wave0.do. Next time, load with File → Load → Macro File to skip re-adding signals. Each project’s starter pack includes a waveN.do you can use directly.

Iterating

After editing source:

1. Re-select the changed files in the Project tab and Compile Selected.
2. Simulate → End Simulation, then re-launch the simulation.
3. Run again.

Tips

• Internal signals are visible. Unlike LabsLand or the Autograder, ModelSim lets you probe wires inside submodules. This is the fastest way to localize bugs.
• Don’t rely on the Autograder for debugging. Reproduce a failing case in ModelSim with the same input pattern, look at the waveform, and trace the bug to its source.
• Read the transcript pane when something compiles or simulates oddly, compiler errors and warnings often point to the issue (uninitialized regs, port-width mismatches, etc.).